1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a method of forming a lower storage node and contact for a capacitor on a dynamic random access memory (DRAM).
2. Description of the Prior Art
DRAM devices are used for storing digital information. A high density DRAM comprises millions of memory cells. Each memory cell consists of a metal-oxide semiconductor field-effect transistor (MOSFET) serving as a pass transistor, and a capacitor used to store electric charge. The electric charge is read and written through an access composed of the storage node of the capacitor, the conductive plug which fills the contact hole, and the drain of the MOSFET.
However, with the rapidly increasing integration density of DRAM, allowable size of the contact hole has shrunk markedly; contact hole diameters of 0.1 .mu.m are not uncommon. But in order to satisfy the requirement for short refresh time, the capacitive value of the capacitor must be larger than 2.5 fF, and the height of the capacitor must therefore be greater than 10 k .ANG.. Because the polysilicon or amorphous silicon contact plug that fills the contact hole must have very small diameter, and the storage node which it structurally fastens and supports must be relatively large, there is a very serious problem of contact plug breakage during subsequent wafer cleaning processes. Such breakage is termed storage node collapse.
Please refer to FIG. 1 through FIG. 9. FIG. 1 through FIG. 9 show cross-section views of prior art for forming a contact hole 26 and a lower storage node 32. As shown in FIG. 1, a semiconductor wafer 10 comprises a substrate 12 and a silicon oxide layer 14 covering the substrate 12. A raised landing pad 16 made of polysilicon is positioned on a predetermined region of the substrate 12 to serve as an electrical connector. Two parallel bit lines 18 made of polysilicon are embedded in silicon oxide layer 14 to serve as a transmission way for digital information.
As shown in FIG. 2, the prior art method performs a low pressure chemical vapor deposition (LPCVD) process to form a first polysilicon layer 20 with thickness of 1.6 k.ANG. on the silicon oxide layer 14. Conditions of the LPCVD process include: silane (SiH4) as reactive gas, process temperature of 575.about.600.degree. C., and process pressure of 0.3.about.0.6 torr. As shown in FIG. 3, a photoresist layer 21 is formed on the first polysilicon layer 20. Then, a photolithography process is performed on the photoresist layer 21 to define the position and the size of a recess. A dry etching process is performed to vertically remove the first polysilicon layer 20 at the recess position to form a recess 22 with vertical walls and diameter of about 0.2 .mu.m.
As shown in FIG. 4, a second and similar LPCVD process is performed to form a second polysilicon layer 24 with thickness of 500 .ANG., which covers the first polysilicon layer 20 and the recess 22 uniformly. As shown in FIG. 5, a anisotropic dry etching process is performed to remove the second polysilicon layer 24 from the top of the first polysilicon layer and from the bottom of the recess 22 leaving only a remnant of the second polysilicon layer on the vertical walls of recess 22, forming annular spacer 25. As shown in FIG. 6, an aniostropic dry etching process is performed again to remove the silicon oxide layer 14 within the diameter of spacer 25 downwardly to the landing pad 16 to form a contact hole 26 with a diameter of 0.1 .mu.m.
As shown in FIG. 7, a LPCVD process is performed to form a first conductive layer 28 and fill up the contact hole 26. As shown in FIG. 8, a second conductive layer 30 with thickness greater than 10 k.ANG. is formed on the first conductive layer 28. The first conductive layer 28 and the second conductive layer 30 may be of similar or different silicon material, such as polysilicon or amorphous silicon.
The first conductive layer 28 formed by the LPCVD process has very high resistivity, so a doping process needs to be performed on the first conductive layer to reduce the resistivity. There are two doping methods: one method utilizes an ion implantation process to implant dopants into the first conductive layer 28 and the second conductive layer 30 after their deposition. Another method is to introduce the dopants into the CVD chamber, thereby accomplishing the deposition process and the ion implantation process at the same time.
Finally, as shown in FIG. 9, a photolithography process is performed to define the position and the size of the lower storage node 32, and an anisotropic dry etching process is performed to vertically remove the first conductive layer 28, the second conductive layer 30 and the first polysilicon layer 20 between storage node locations on the silicon oxide layer 14 down to the surface of silicon oxide layer 14 to complete the lower storage node 32.
In the prior art method of forming the contact hole 26 and the lower storage node 32, the spacer 25 serves as a hard mask to form the contact hole 26 with diameter of 0.1 .mu.m. Without such hard masking the present lithography technology cannot form a contact hole with the critical dimension smaller than 0.2.about.0.18 .mu.m.
Please refer to FIG. 10. FIG. 10 is a cross-section diagram of the prior-art lower storage node having collapsed. In order to provide the required capacitance and sufficient charge storage, the height of the lower storage node 32 must be greater than 10 k.ANG..
Since there is little or no bonding between the lower storage node 32 and the silicon oxide layer 14, the fastening and structural connection between the lower storage node 32 and silicon oxide layer 14 depends on the silicon contact plug which fills the contact hole 26. But the diameter of that silicon contact plug is only 0.1 .mu.m, thus it is very easy during the several wafer cleaning processes which are part of the fabrication sequence, for the said silicon contact plug to break on account of stresses due to the vigorous motion of cleaning solution. Structural failure due to such breaking of the said contact plug is called collapse of the lower storage node. The collapsed lower storage node 32 has no electrical connection to the substrate 12, and therefore no capability of information storage.